Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier

ABSTRACT

A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is deposited overlying the substrate layer. The dielectric layer patterned to form interconnect trenches. An optional titanium adhesion layer may be deposited. An aluminum barrier layer is deposited overlying the interior surfaces of the trenches. A second barrier layer, comprising for instance titanium and titanium nitride, is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, the second barrier layer, and the aluminum barrier layer are polished down to the top surface of the dielectric layer to define the copper interconnects, and complete the fabrication of the integrated circuit device.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to the fabrication of semiconductorstructures, and more particularly, to a method to form copperinterconnects using an aluminum layer as gettering agent in the copperdiffusion barrier layer in the manufacture of integrated circuits.

(2) Description of the Prior Art

As integrated circuit feature sizes continue to decrease, it has becomeadvantageous to construct metal connections out of copper instead ofaluminum. Copper has a lower resistivity than aluminum, and thereforecan form higher speed connections for a given line width.

To use copper effectively in an integrated circuit technology, however,the problem of copper diffusion into other materials must be addressed.For example, copper diffuses into common dielectrics, such as silicondioxide, much more easily than does aluminum. This phenomenon can causeelectrical leakage paths and shorts in the completed circuit.

Referring to FIG. 1, a cross-section of a partially completed prior artcopper interconnect structure is shown. Because copper is more difficultto reliably etch than aluminum, a damascene approach is typically usedto form copper interconnects. A substrate layer 10 is depicted. Thesubstrate layer 10 encompasses all underlying layers, devices,junctions, and other features that have been formed prior to thedeposition and definition of metal traces (Cu, Al, W, etc.,) 18 in anisolation layer 14. A dielectric layer 22 overlies the isolation layer14 and the copper traces 18.

Via openings are formed in the dielectric layer 22 to expose the topsurfaces of the conductive traces 18. The via openings are typicallyetched using a reactive ion etch and then cleaned. In the process ofetching and cleaning the vias, however, copper from the copper traces 18can contaminate the sidewalls 26 of the vias.

Referring now to FIG. 2, a barrier layer 30 is deposited overlying thedielectric layer 22 and the exposed conductive traces 18. A copper layerwill subsequently be deposited overlying the barrier layer 30 to fillthe vias. The purpose of the barrier layer 30 is to prevent copper outdiffusion into the dielectric layer 22 while establishing a lowresistance contact path to the underlying copper traces 18. This barrierlayer 30 is commonly comprised of tantalum, tantalum nitride or bothtantalum and tantalum nitride.

The use of tantalum and tantalum nitride for the diffusion barriercreates two problems however. First, while the tantalum enhances thefield adhesion for the copper layer, the chemical inertness andmechanical hardness of tantalum makes this barrier layer difficult toplanarize in later process steps. Second, the tantalum and tantalumnitride barrier layer 30 cannot act as a copper plating catalyst.Therefore, a copper seed layer has to be deposited for subsequent copperplating by either electrochemical copper plating or electroless copperplating.

Unfortunately, the commonly used technology for depositing the tantalum,tantalum nitride, and copper seed layer is physical vapor deposition(PVD). The PVD technology provides relatively poor step coverage.Therefore, a substantial minimum thickness of barrier layer 30 isrequired. When coupled with the requirement of the additional copperseed layer, the process of the prior art is not extendible to the verysmall feature sizes of the future technology.

Several prior art approaches attempt to improve the barrier layer incopper interconnect processes for use in integrated circuitmetalization. U.S. Pat. No. 5,695,810 to Dubin et al discloses a processto form a barrier layer composed of cobalt tungsten phosphide (CoWP) forcopper interconnects. The prior art section also discusses barrierlayers of Ta, Mo, W, TiW, TiN, WN, TiSiN, Ni, Co, and Ni—Co alloys. U.S.Pat. No. 5,801,100 to Lee et al teaches the use of a nickel containinglayer as a copper diffusion barrier in an interconnect process. U.S.Pat. No. 5,821,168 to Jain discloses a process to form copper structureswhere an insulating layer is nitrided to form a barrier layer. Anadhesion layer of silicon, silicon germanium, germanium, magnesium, ortitanium is then deposited before the electroplating of copper. U.S.Pat. No. 5,674,787 to Zhao et al teaches a process to selectivelydeposit copper to form interconnects. Barrier layers of TiN, TiW, Ta,TaN, and WN are disclosed.

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide an effectiveand very manufacturable method of fabricating integrated circuits withcopper interconnects.

A further object of the present invention is to provide a method offabricating copper interconnects with a diffusion barrier partiallycomprising aluminum.

A yet further object of the present invention is to form an improvedbarrier layer comprising aluminum and a second barrier material wherethe improved barrier layer further inhibits copper diffusion.

Another yet further object of the present invention is to form animproved barrier layer comprising aluminum and a second barrier materialwhere the improved barrier layer has a much lower resistance.

Another further object of the present invention is to form an improvedbarrier layer comprising aluminum and a second barrier material wherethe second barrier layer provides a catalyst layer for seedlesselectrochemical or electroless copper plating.

In accordance with the objects of this invention, a new method offabricating an integrated circuit with copper interconnects is achieved.A substrate layer is provided encompassing all underlying layers,devices, and junctions. Metal traces—Cu, Al, W, etc., are provided in afirst dielectric layer. A second dielectric layer is deposited overlyingthe metal traces and the first dielectric layer. The second dielectriclayer is patterned to form interconnect trenches for single or dualdamascene interconnect structures. An aluminum barrier layer isdeposited overlying the second dielectric layer and the exposed metaltraces. A second barrier layer is deposited overlying the aluminumbarrier layer. A copper layer is deposited overlying the second barrierlayer and filling the interconnect trenches. The copper layer, secondbarrier layer, and aluminum barrier layer are polished down to the topsurface of the second dielectric layer to define copper interconnects.An encapsulation layer is deposited overlying the copper interconnectsand the second dielectric layer. A passivation layer is depositedoverlying the encapsulation layer to complete the fabrication of theintegrated circuit device.

In addition, in accordance with the objects of this invention, a newmethod of fabricating an integrated circuit with copper interconnects isachieved. A substrate layer is provided encompassing all underlyinglayers, devices, and junctions. Metal traces—Cu, Al, W, etc., areprovided in a first dielectric layer. A second dielectric layer isdeposited overlying the metal traces and the first dielectric layer. Thesecond dielectric layer is patterned to form interconnect trenches forsingle or dual damascene interconnect structures. A titanium adhesionlayer is deposited overlying the second dielectric layer and the exposedmetal traces. An aluminum barrier layer is deposited by a hightemperature process overlying the titanium adhesion layer. A secondbarrier layer is deposited overlying the aluminum barrier layer. Acopper layer is deposited overlying the second barrier layer and fillingthe interconnect trenches. The copper layer, second barrier layer,aluminum barrier layer and titanium adhesion layer are polished down tothe top surface of the second dielectric layer to define copperinterconnects. An encapsulation layer is deposited overlying the copperinterconnects and the second dielectric layer. A passivation layer isdeposited overlying the encapsulation layer to complete the fabricationof the integrated circuit device.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of thisdescription, there is shown:

FIGS. 1 and 2 schematically illustrate in cross-section a partiallycompleted prior art integrated circuit using a conventional barrierlayer.

FIGS. 3 through 9 schematically illustrate in cross-sectionalrepresentation a first embodiment of the present invention used tocreate copper interconnects.

FIGS. 10 through 15 schematically illustrate in cross-sectionalrepresentation a second embodiment of the present invention used tocreate copper interconnects.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now more particularly to FIG. 3, there is illustrated aportion of a partially completed integrated circuit. In the preferredembodiments, the present invention will be used to create copperinterconnects. In the illustrations of the first and second embodiments,the present invention is described for a single damasceneinterconnection. It should be obvious to those skilled in the art thatthe essential ideas of the invention could be applied to dual damasceneinterconnects with little, or no, changes. It will be understood bythose skilled in the art that the invention could be applied to theformation of other copper structures.

In the first embodiment of the present invention, a substrate 40 isprovided encompassing all underlying layers, devices, junctions, andother features that have been formed prior to the deposition of a firstdielectric layer 44. Metal traces (Cu, Al, W, etc.,) 48 are provided inthe first dielectric layer 44 to illustrate the present invention usedin the formation of interconnects connected to underlying traces. Asecond dielectric layer 52 is deposited overlying the metal traces 48and the first dielectric layer 44. The second dielectric layer 52 ispreferably composed of an oxide such as a low k-value fluorinatedsilicate glass (FSG) which is planarized after deposition. Preferably,the second dielectric layer 52 is deposited to a thickness of betweenabout 4,000 Angstroms and 20,000 Angstroms, depending, for example, ifthe interconnects are single or dual damascene.

Referring now to FIG. 4, the second dielectric layer 52 is etchedthrough to the underlying metal traces 48 where the dielectric layer 52is not protected by a photoresist mask which is not shown. This etchingstep forms the interconnect trenches. The interconnect trenches areetched by a conventional reactive ion etch (RIE). As illustrated in theprior art analysis, this etching step can create copper contamination 56on the sidewalls of the interconnect trenches.

Referring now to FIG. 5, an important aspect of the present invention isdescribed. An aluminum barrier layer 60 is deposited overlying thesecond dielectric layer 52 and the exposed metal traces 48. The aluminumbarrier layer 60 is herein used as an addition to a conventional barriersuch as titanium, titanium nitride, or both titanium and titaniumnitride, which will be deposited subsequently. The conventional barrieris a good thermal barrier. However, it may not be an adequate barrier tocopper ion diffusion. The addition of the aluminum barrier layer 60creates a superior composite barrier due to the special properties ofthe aluminum.

First, aluminum can form a solid-state solution with copper at the Al—Cuinterface. Because of the high solubility of copper in aluminum, Cu ionsand atoms do not diffuse through the aluminum barrier layer 60 from akinetic standpoint. Second, aluminum also acts as a gettering agent forcopper. Any free copper ions or atoms in the area of the aluminumbarrier layer 60 will be absorbed into the aluminum. This provides asolution to the problem of copper contamination 56 of the trenchsidewalls. The free copper is gettered by the aluminum barrier layer 60and does not then act as a source of future diffusion problems in thesecond dielectric layer 52. Finally, the low resistivity of aluminumprovides a low resistance contact path between the conductive traces 48and the subsequently formed copper interconnects.

The aluminum barrier layer 60 may be deposited using either chemicalvapor deposition or physical vapor deposition. The aluminum barrierlayer 60 so formed has a thickness of between about 50 Angstroms and 300Angstroms.

In addition to aluminum, it may be possible to extend the approach ofthe present invention to other metallurgical materials. For example,other low resistivity metals, such as gold, silver, zinc, cobalt, nickeland tungsten, could be used instead of aluminum to create enhancedcomposite copper barriers.

Referring now to FIG. 6, another important part of the present inventionis shown. A second barrier layer 64 is deposited overlying the aluminumbarrier layer 60. The second barrier layer 64 serves two purposes.First, the second barrier layer 64 inhibits copper thermalout-diffusion. Second, the second barrier layer 64 may serve as acatalyst for the seedless plating of the copper layer. The secondbarrier layer 64 may be comprised of one of several different refractorymetal nitrides and silicon nitrides, including TiN, MoN, WN, MoSiN, andWSiN. In this preferred embodiment, the second barrier layer 64 iscomposed of a combined layer of titanium and titanium nitride (Ti/TiN).The combined layer of titanium and titanium nitride may be depositedusing either a chemical vapor deposition (CVD), a ionized metal plating(IMP), or a physical vapor deposition (PVD) process. The second barrierlayer 64 so formed has a thickness of between about 50 Angstroms and 300Angstroms.

Referring now to FIG. 7, a copper layer 68 is deposited overlying thesecond barrier layer 64 and filling the interconnect trenches. Thecopper layer 68 may be deposited using chemical vapor deposition (CVD),physical vapor deposition (PVD), electrochemical copper plating, or anelectroless copper plating. In the preferred embodiment, the copperlayer 68 is deposited using an electrochemical copper plating operationto a thickness of between about 6,000 Angstroms and 20,000 Angstroms.The thickness depends on whether a single or dual damascene interconnectis formed. The second barrier layer 64 may act as a catalyst to allowthe plating operation to proceed without the expensive formation of acopper seed layer.

Referring now to FIG. 8, the copper layer 68, second barrier layer 64,and aluminum barrier layer 60 are polished down to the top surface ofthe second dielectric layer 52 to define copper interconnects. This stepis accomplished via a conventional chemical mechanical polishing (CMP)operation. In this step, the advantage of using only aluminum and theTi/TiN layer is realized. It is easier to reliably polish down theselayers when compared to the conventional tantalum-based barrier layerused in the prior art. Thus, the present invention improves the processcapability when compared to the prior art.

Referring now to FIG. 9, an encapsulation layer 70 is depositedoverlying the copper interconnects and the second dielectric layer 52.The encapsulation layer 70 is preferably composed of silicon nitridedeposited by chemical vapor deposition (CVD) to a thickness of betweenabout 300 Angstroms and 2,000 Angstroms. The encapsulation layer 70provides a final copper diffusion barrier over the top of the copperinterconnects. A passivation layer 72, of plasma nitride, is thendeposited overlying the encapsulation layer 70 to complete thefabrication of the integrated circuit device.

Referring now to FIG. 10, a second preferred embodiment of the presentinvention is illustrated. After the formation of the interconnecttrenches in FIG. 4, an additional process step is inserted into thesequence. As shown in FIG. 10, a titanium adhesion layer 76 is depositedoverlying the second dielectric layer 52 and the exposed metal traces48. The titanium adhesion layer 76 is used if the aluminum will bedeposited by a high temperature process. The titanium adhesion layer 76improves the adhesion of aluminum deposited by this process. In thispreferred embodiment, the titanium adhesion layer 76 is deposited byionized metal plating (IMP) or by physical vapor deposition (PVD). Thetitanium adhesion layer 76 so formed has a thickness of between about 30Angstroms and 200 Angstroms.

Referring now to FIG. 11, the second preferred embodiment processcontinues in the same sequence as the first preferred embodiment. Thealuminum barrier layer 80 is deposited overlying the titanium adhesionlayer 76. In this embodiment, the aluminum barrier layer 80 is depositedby physical vapor deposition (PVD) or chemical vapor deposition (CVD).This process is chosen to achieve improved step coverage of the aluminumover surface features. The aluminum barrier layer 80 so formed has athickness of between about 50 Angstroms and 300 Angstroms.

Referring now to FIG. 12, a second barrier layer 84 is depositedoverlying the aluminum barrier layer 80. The second barrier layer 84 maybe comprised of one of several different refractory metal nitrides andsilicon nitrides, including TiN, MoN, WN, MoSiN, and WSiN. In thispreferred embodiment, the second barrier layer 84 is composed of acombined layer of titanium and titanium nitride (Ti/TiN) deposited bychemical vapor deposition (CVD), ionized metal plating (IMP), orphysical vapor deposition (PVD). The second barrier layer 84 so formedhas a thickness of between about 30 Angstroms and 300 Angstroms.

Referring now to FIG. 13, a copper layer 88 is deposited overlying thesecond barrier layer 84 and filling the interconnect trenches. Thecopper layer 88 may be deposited using chemical vapor deposition (CVD),physical vapor deposition (PVD), electrochemical copper plating, orelectroless copper plating. In this preferred embodiment, the copperlayer 88 is deposited using electrochemical copper plating to athickness of between about 6,000 Angstroms and 20,000 Angstroms. Thethickness of the copper layer 88 depends on whether a single or dualdamascene structure is formed.

Referring now to FIG. 14, the copper layer 88, second barrier layer 84,aluminum barrier layer 80, and titanium adhesion layer 76 are polisheddown to the top surface of the second dielectric layer 52 to definecopper interconnects. This step is accomplished via a conventionalchemical mechanical polishing (CMP) operation. As before, the advantageof using only titanium, aluminum and the Ti/TiN layer is realized. It iseasier to reliably polish down these layers when compared to theconventional tantalum-based barrier layer of the prior art. Thus, thepresent invention improves the process capability when compared to theprior art.

Referring now to FIG. 15, an encapsulation layer 90 is depositedoverlying the copper interconnects and the second dielectric layer 52.The encapsulation layer 90 is preferably composed of silicon nitridedeposited by chemical vapor deposition (CVD) to a thickness of betweenabout 300 Angstroms and 2,000 Angstroms. The encapsulation layer 90provides a final copper diffusion barrier over the top of the copperinterconnects. A passivation layer 92, of plasma nitride, is thendeposited overlying the encapsulation layer 90 to complete thefabrication of the integrated circuit device.

The process of the present invention provides a very manufacturablemethod for fabricating copper interconnects with a copper diffusionbarrier layer and gettering agent comprised of aluminum in thefabrication of an integrated circuit device.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

What is claimed is:
 1. A method to form copper interconnects in thefabrication of an integrated circuit device comprising: providing asubstrate layer encompassing all underlying layers, devices, junctions,and other features; depositing a dielectric layer overlying saidsubstrate layer; patterning said dielectric layer to form interconnecttrenches where copper interconnects are planned; depositing an aluminumbarrier layer overlying said dielectric layer and the internal surfacesof said interconnect trenches; depositing a second barrier layeroverlying said aluminum barrier layer; depositing a copper layeroverlying said second barrier layer and filling said interconnecttrenches; polishing down said copper layer, said aluminum barrier layer,and said second barrier layer to the top surface of said dielectriclayer and thereby defining said copper interconnects; and completing thefabrication of the integrated circuit device.
 2. The method according toclaim 1 wherein said aluminum barrier layer is deposited to a thicknessof between about 50 Angstroms and 300 Angstroms.
 3. The method accordingto claim 1 further comprising depositing a titanium adhesion layeroverlying said dielectric layer and the interior surfaces of saidinterconnect trenches prior to depositing said aluminum barrier layer.4. The method according to claim 1 wherein said interconnect trenchesare single damascene structures.
 5. The method according to claim 1wherein said interconnect trenches are dual damascene structures.
 6. Themethod according to claim 1 wherein said second barrier layer comprisesone of the group containing: TiN, MoN, WN, MoSiN, and WSiN.
 7. Themethod according to claim 1 wherein said second barrier layer comprisesa composite layer of titanium and titanium nitride deposited to athickness of between about 50 Angstroms and 300 Angstroms.
 8. The methodaccording to claim 1 wherein said step of depositing a copper layer isby electrochemical plating depositing copper to a thickness of betweenabout 6,000 Angstroms and 20,000 Angstroms.
 9. A method to form copperinterconnects in the fabrication of an integrated circuit devicecomprising: providing a substrate layer encompassing all underlyinglayers, devices, junctions, and other features; providing first metaltraces in a first dielectric layer overlying said substrate; depositinga second dielectric layer overlying said first metal traces and saidfirst dielectric layer; patterning said second dielectric layer to forminterconnect trenches to expose top surfaces of said metal traces wherecopper interconnects are planned; depositing an aluminum barrier layeroverlying said second dielectric layer, the internal surfaces of saidinterconnect trenches, and said exposed top surfaces of said metaltraces; depositing a second barrier layer comprising titanium andtitanium nitride overlying said aluminum barrier layer; depositing acopper layer overlying said second barrier layer and filling saidinterconnect trenches; polishing down said copper layer, said secondbarrier layer, and said aluminum barrier layer to the top surface ofsaid second dielectric layer and thereby defining said copperinterconnects; and completing the fabrication of the integrated circuitdevice.
 10. The method according to claim 9 wherein said metal tracescomprise at least one of the group containing copper, aluminum, andtungsten.
 11. The method according to claim 9 wherein said aluminumbarrier layer is deposited to a thickness of between about 50 Angstromsand 300 Angstroms.
 12. The method according to claim 9 furthercomprising depositing a titanium adhesion layer overlying said seconddielectric layer, said internal surfaces of said interconnect trenches,and said exposed top surfaces of said metal traces prior to depositingsaid aluminum barrier layer.
 13. The method according to claim 9 whereinsaid interconnect trenches are single damascene structures.
 14. Themethod according to claim 9 wherein said interconnect trenches are dualdamascene structures.
 15. The method according to claim 9 wherein saidsecond barrier layer is deposited to a thickness of between about 50Angstroms and 300 Angstroms.
 16. The method according to claim 9 whereinsaid step of depositing a copper layer is by electrochemical platingdepositing copper to a thickness of between about 6,000 Angstroms and20,000 Angstroms.
 17. A method to form copper interconnects in thefabrication of an integrated circuit device comprising: providing asubstrate layer encompassing all underlying layers, devices, junctions,and other features; providing first metal traces in a first dielectriclayer overlying said substrate; depositing a second dielectric layeroverlying said first metal traces and said first dielectric layer;patterning said second dielectric layer to form interconnect trenches toexpose top surfaces of said metal traces where copper interconnects areplanned; depositing a titanium adhesion layer overlying said seconddielectric layer, the internal surfaces of said interconnect trenches,and said exposed top surfaces of said metal traces; depositing analuminum barrier layer overlying said titanium adhesion layer;depositing a second barrier overlying said aluminum barrier layer;depositing a copper layer overlying said second barrier layer andfilling said interconnect trenches; polishing down said copper layer,said second barrier layer, said aluminum barrier layer, and saidtitanium adhesion layer to the top surface of said second dielectriclayer and thereby defining said copper interconnects; and completing thefabrication of the integrated circuit device.
 18. The method accordingto claim 17 wherein said metal traces comprise at least one of the groupcontaining copper, aluminum, and tungsten.
 19. The method according toclaim 17 wherein said aluminum barrier layer is deposited to a thicknessof between about 50 Angstroms and 300 Angstroms.
 20. The methodaccording to claim 17 wherein said titanium adhesion layer is depositedto a thickness of between about 30 Angstroms and 200 Angstroms.
 21. Themethod according to claim 17 wherein said second barrier layer comprisesone of the group containing: Ti/TIN, TiN, MoN, WN, MoSiN, and WsiN andis deposited to a thickness of between about 50 Angstroms and 300Angstroms.
 22. The method according to claim 17 wherein said step ofdepositing a copper layer is by electrochemical plating and depositscopper to a thickness of between about 6,000 Angstroms and 20,000Angstroms.